(A) Field of the Invention
The present invention relates to a method for preparing a shallow trench isolation, and more particularly, to a method for preparing a shallow trench isolation without using a silicon nitride liner layer but having a silicon oxide layer with a larger thickness at the bottom portion than at the upper portion of the trench.
(B) Description of the Related Art
Conventional integrated circuit fabrication processes use a local oxidation of silicon (LOCOS) technique or shallow trench isolation (STI) technique to electrically isolate wafer-mounted electronic devices from each other, so as to avoid short circuits and cross interference. Due to the LOCOS technique's forming a field oxide layer covering a larger wafer area and also because it forms a “bird's beak” pattern, advanced integrated circuit fabrication generally selects the STI technique to electrically isolate electronic devices.
FIG. 1 to FIG. 4 illustrate a method for preparing a shallow trench isolation 10 according to the prior art. First, a mask 15 having several openings 18 is formed on a silicon substrate 12, with the mask 15 including a pad oxide layer 14 and a pad nitride layer 16. Subsequently, an anisotropic etching process is performed to form a plurality of trenches 20 in the silicon substrate 12 under the openings 18, and a thermal oxidation process is then performed to form a wall oxide layer 24 on the bottom surface and inner sidewall of the trenches 20, as shown in FIG. 2. The trenches 20 surround an active area 22.
Referring to FIG. 3, a silicon nitride liner layer 26 is formed to cover the wall oxide layer 24 and the pad nitride layer 16, and a silicon oxide liner layer 28 is then formed to cover the silicon nitride liner layer 26. In particular, the silicon nitride liner layer 26 is used to prevent the inner sidewall of the trenches 20, i.e., the silicon substrate 12, from over oxidation during the subsequent thermal oxidation process. Subsequently, a dielectric layer 30 is formed to fill the trenches 20, and the chemical mechanical polishing process is then performed to remove a portion of the silicon nitride liner layer 26 and the silicon oxide liner layer 28 from the silicon nitride layer 16 to complete the shallow trench isolation 10, as shown in FIG. 4. However, the prior art uses the silicon nitride liner layer 26, which is likely to form defects serving as electron-trapping sites, and therefore is not applicable to the preparation of the flash memory.